Global Optimization of Asynchronous Logic Networks for Manufacturing Physical CircuitsTechnology #m06-098
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“Lead Inventor: Steven M. Nowick, PhD
CAD (Computer Aided Design) Flow Timing Hazards in Process, Temperature, and Voltage Variations Avoiding and/or removing timing hazards is challenging in synchronous CAD flows as process, temperature, and voltage variations become significant in deep submicron design (for integrated circuits). One attractive alternative is the use of asynchronous circuits that can accommodate timing discrepancies as well as consume less power, reduce electromagnetic interference, improve robustness to parameter variations, and provide modularity of design. However, little CAD support and area overhead in such a design style continue to block adoption of these robust methodologies.
Optimized Asynchronous Dual-Rail Circuits for Designing and Manufacturing Physical Circuits This technology provides an algorithm that optimizes asynchronous dual-rail circuits (e.g. NULL conventional logic circuits) with respect to area, number of fully-expanded logic gates, or delay of the circuit by local relaxation of input completeness. In addition, this technology provides a computer-readable medium containing a set of instructions to perform a method for forming an asynchronous logic network, as well as a system for forming an asynchronous logic network.
• Used for forming an asynchronous logic network for manufacturing a physical circuit
For physical circuit design:
• Avoids and/or removes timing hazards
• Reduces power consumption and electromagnetic interference
• Improves robustness to parameter variations (e.g. process, temperature, and voltage)
• Allows modular approach
Patent Status: Patent Pending (WO/2007/139928)
Publications: C. Jeong and S. Nowick, ”“Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation,”“ IEEE 2007
Licensing Status: Available for Licensing and Sponsored Research Support